MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 619

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 26-23
occur if a pod device is connected to the target BKGD pin and the target is already executing a BDC
command. Consider that the target CPU is executing a pending BDC command at the exact moment the
pod is being connected to the BKGD pin. In this case, an ACK pulse is issued at the same time as the SYNC
command. In this case there is an electrical conflict between the ACK speedup pulse and the sync pulse.
Because this is not a probable situation, the protocol does not prevent this conflict from happening.
The hardware handshake protocol is enabled by the ACK_ENABLE command and disabled by the
ACK_DISABLE command. It also allows for pod devices to choose between the hardware handshake
protocol or the software protocol that monitors the XCSR status byte. The ACK_ENABLE and
ACK_DISABLE commands are:
Freescale Semiconductor
(TARGET MCU)
DRIVES SYNC
•
TARGET MCU
TO BKGD PIN
BKGD PIN
BDC CLOCK
DRIVES TO
BKGD PIN
BKGD PIN
ACK_ENABLE — Enables the hardware handshake protocol. The target issues the ACK pulse
when a CPU command is executed. The ACK_ENABLE command itself also has the ACK pulse
as a response.
HOST
a shows a conflict between the ACK pulse and the sync request pulse. This conflict could
READ_MEM.B
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
READ_MEM.B CMD
IS ABORTED BY THE SYNC REQUEST
(NOT TO SCALE)
Figure 26-22. ACK Abort Procedure at the Command Level
HOST
Figure 26-23. ACK Pulse and SYNC Request Conflict
ADDRESS[23-0]
HOST SYNC REQUEST PULSE
TARGET
BDC DECODES
AND CPU TRYS TO EXECUTE
THE READ_MEM.B CMD
ACK PULSE
16 CYCLES
HOST AND TARGET
DRIVE TO BKGD PIN
AT LEAST 128 CYCLES
READ_XCSR_BYTE
ELECTRICAL CONFLICT
HIGH-IMPEDANCE
SYNC RESPONSE
FROM THE TARGET
(NOT TO SCALE)
HOST
TARGET
NEW BDC COMMAND
Version 1 ColdFire Debug (CF1_DEBUG)
NEW BDC COMMAND
HOST
SPEEDUP PULSE
TARGET
26-55