MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 591

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

number (CRN)
Core register
26.4
26.4.1
This section provides details on the background debug serial interface controller (BDC) and the BDM
command set.
The BDC provides a single-wire debug interface to the target MCU. As shown in the Version 1 ColdFire
core block diagram of
and the remaining debug modules, including the ColdFire background debug logic, the real-time debug
hardware, and the PST/DDATA trace logic. This interface provides a convenient means for programming
the on-chip flash and other non-volatile memories. The BDC is the primary debug interface for
development and allows non-intrusive access to memory data and traditional debug features such as
run/halt control, read/write of core registers, breakpoints, and single instruction step.
Features of the background debug controller (BDC) include:
Freescale Semiconductor
0x1A
0x1B
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
•
•
•
•
•
•
•
•
Single dedicated pin for mode selection and background communications
Special BDC registers not located in system memory map
SYNC command to determine target communications rate
Non-intrusive commands for memory access
Active background (halt) mode commands for core register access
GO command to resume execution
BACKGROUND command to halt core or wake CPU from low-power modes
Oscillator runs in stop mode, if BDM enabled
Functional Description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
10[1:0]
26[1:0]
42[1:0]
58[1:0]
Background Debug Mode (BDM)
TB #05[3:0]
TB #21[3:0]
TB #37[3:0]
TB #53[3:0]
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
TB #00
TB #16
TB #32
TB #48
Figure
TB #11
TB #27
TB #43
TB #59
Figure 26-15. PST Trace Buffer Entries and Locations
TB #06
TB #22
TB #38
TB #54
26-1, the BDC module interfaces between the single-pin (BKGD) interface
TB #01
TB #17
TB #33
TB #49
TB #12
TB #28
TB #44
TB #60
TB #07
TB #23
TB #39
TB #55
TB #02
TB #18
TB #34
TB #50
TB #13
TB #29
TB #45
TB #61
TB #08
TB #24
TB #40
TB #56
TB #03
TB #19
TB #35
TB #51
Version 1 ColdFire Debug (CF1_DEBUG)
TB #14
TB #30
TB #46
TB #62
9
8
TB #09
TB #25
TB #41
TB #57
7
6
TB #04
TB #20
TB #36
TB #52
5
4
TB #15
TB #31
TB #47
TB #63
3
TB #10[5:2]
TB #26[5:2]
TB #42[5:2]
TB #58[5:2]
2
26-27
05[5:4]
21[5:4]
37[5:4]
53[5:4]
1
0