MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 420

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Independent Robust Real Time Clock (IRTC)
17.7
17.7.1
17.7.2
17.7.3
17-36
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This is the initial flow that needs to be done after every power-on reset
CPU sets the date and time into the IRTC registers
CPU sets other control information needed for IRTC to function
CPU enables the various interrupts and alarm time as per its requirements
CPU stores in the Standby RAM inside IRTC, any critical data needed to be preserved in the event
of main voltage loss. This can be done during normal operation too.
IRTC has configuration bits that can be used for application dependent protocol and these bits need
to retain state during mains voltage removal. These are programmed by the CPU
CPU enables the tamper control bits. If not, this is done after 15 seconds of power on.
Once the complete configuration of IRTC is done, the CPU should put the IRTC in write protect
state. If not, this is automatically done after 15 seconds of power on.
During the Normal Operation of IRTC, all write accesses to registers are blocked. Only by
following the unlock sequence mentioned in Register Description can CPU get the write access and
modify the contents on the registers.
During the normal operation, any interrupt might occur or the Standby RAM needs to be updated
or some control information needs to change.
Any such operation should be preceded by the Unlock Sequence mentioned above.
Interrupts can occur when the time in counters match the value in alarm registers or when a
sampling timer expires or a tamper is detected
CPU should service these interrupts and then put the IRTC back in write-protect mode. If not, write
protect is enabled 2 seconds after unlock.
Standby operation is defined as operation of IRTC on battery voltage and no MCU voltage
Whenever the main voltage falls below a certain threshold, the system switches to battery power
and IRTC functions normally.
The switching of power and detection of low voltage threshold of MCU voltage is done in analog
blocks outside the IRTC design. Refer to
Whenever the MCU voltage is restored, the IRTC switches over to this power
If the battery drains out and when the power is supplied again to IRTC (by new battery or CPU
power), a power on reset is sent to IRTC and all registers are reset. Application needs to signal for
re-calibration of the IRTC.
Modes of Operation (Based on Data Flow)
IRTC Configuration
IRTC Normal Operation
IRTC Standby Operation
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Section 17.1.1, “IRTC Power Supply
Freescale Semiconductor
Source,” for details.