MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 316

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Serial Peripheral Interface (SPI16)
13-30
SPIxC1=0x54(%01010100)
SPIxC2 = 0xC0(%11000000)
SPIxBR = 0x00(%00000000)
SPIxS = 0x00(%00000000)
SPIxMH = 0xXX
SPIxML = 0xXX
SPIxDH = 0xxx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6:4
Bit 3:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register will be
ignored.
Holds bits 0–7 of the hardware match buffer.
In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by the
receive buffer.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
SPMIE
SPIMODE
MODFEN
BIDIROE
SPISWAI
SPC0
SPRF
SPMF
SPTEF
MODF
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 0
= 1
= 1
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 000
= 0000
= 0
= 0
= 0
= 0
= 0
Disables receive and mode fault interrupts
Enables the SPI system
Disables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
SPI hardware match interrupt enabled
Configures SPI for 16-bit mode
Unimplemented
Disables mode fault function
SPI data I/O pin acts as input
Unimplemented
SPI clocks operate in wait mode
uses separate pins for data input and output
Unimplemented
Sets prescale divisor to 1
Sets baud rate divisor to 2
Flag is set when receive data buffer is full
Flag is set when SPIMH/L = receive data buffer
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
Unimplemented
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