MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 349

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3.8
Freescale Semiconductor
ALERTEN
SIICAEN
reserved
TCKSEL
Reset
SHTF
FACK
Field
SLTF
7
6
5
4
3
2
W
R
FACK
IIC SMBus Control and Status Register (IICSMB)
Fast NACK/ACK enable — For SMBus Packet Error Checking, CPU should be able to issue an ACK or NACK
according to the result of receiving data byte.
0 ACK or NACK will be sent out on the following receiving data byte.
1 Writing an 0 to TXAK after receiving data byte will generate an ACK; Writing an 1 to TXAK after receiving data
byte will generate a NACK
SMBus Alert Response Address Enable — The ALERTEN bit enables or disable SMBus alert response
address.
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled.
Second IIC Address Enable — The SIICAEN bit enables or disable SMBus device default address.
0 IIC Address Register 2 matching is disabled.
1 IIC Address Register 2 matching is enabled.
Time Out Counter Clock Select— This bit selects the clock sources of Time Out Counter
0 Time Out Counter counts at bus/64 frequency
1 Time Out Counter counts at the bus frequency
SCL Low Timeout Flag — This read-only bit is set to logic 1 when IICSLT loaded non zero value (LoValue) and
a SCL Low Time Out occurs. This bit is cleared by software, by writting a logic 1 to it
0 No LOW TIME OUT occurs.
1 A LOW TIME OUT occurs.
Note: LOW TIME OUT function is disabled when IIC SCL LOW TIMER OUT register is set to zero
SCL High Timeout Flag — This read-only bit is set to logic 1 when SCL and SDA are held high more than clock
* LoValue/512, which indicates the Bus Free. This bit is cleared automatically.
0 No HIGH TIMEOUT occurs.
1 An HIGH TIMEOUT occurs.
0
7
1. A master can assume that the bus is free if it detects that the clock and
data signals have been high for greater than THIGH,MAX, however, the
SHTF will rise in bus transmission process but bus idle state.
2. When TCKSEL=1 there is no meaning to monitor SHTF since the bus
speed is too high to match the protocol of SMBus.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
= Unimplemented or Reserved
ALERTEN
Figure 15-8. IIC SMBus Control and Status Register (IICSMB)
0
6
Table 15-9. IICSMB Field Descriptions
SIICAEN
0
5
TCKSEL
NOTE
0
4
NOTE
Description
SLTF
0
3
SHTF
0
2
Inter-Integrated Circuit (IIC)
1
0
0
0
15-11