MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 400

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Independent Robust Real Time Clock (IRTC)
17.5.9
17-16
OFF_CHIP_CL
DURATION
TAMPER
DETECT
Reset Value
Reset Value
BCDEN
14–13
Field
SWR
12–9
15
K
8
7
IRTC_CTRL
Bit Type
Bit Type
Field
Field
IRTC Control Register (IRTC_CTRL)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Oscillator Clock Output Enable. This bit controls the buffered IRTC oscillator clock to be output from the
IRTC block. This is mainly needed for 8-bit MCUs and 32-bit Coldfire V1s where it is used by the ICS block
of the MCU.
‘1’ – Clock Output Enabled
‘0’ – Clock Output Disabled
Off-chip Clock Output Enable. Needed mostly for 8-bit MPUs. This bit controls the clock to be output from
the IRTC block for external use.
“00” – No clock is output
“01” – Compensated 1 Hz clock output
“10” – Buffered Oscillator clock output
“11” – Reserved. Do not use.
Tamper Detect Duration. This bit indicates the number of oscillator clocks for which the tamper_detect
signal should remains stable before being detected as a tamper. These bits are used by the tamper filtering
operation.
“0” – Filtering operation disabled
“1” to “15” – number of 32kHz oscillator clocks to be counted when tamper is asserted
With the tamper duration set to Zero any tamper detected on the tamper pins will directly set the tamper
status & interrupt bits. Caution is required when making the tamper filter duration equal to 0 as any glitches
on the tamper pins will cause a tamper interrupt.
Software Reset. This is a self clearing bit. It automatically gets cleared on the next clock after write.
‘1’ – Software Reset
‘0’ – No Software Reset
Software reset clears the contents of alarm, interrupt (status & enable except tamper) registers and has
no effect on DST, Standby RAM, Up counter, time, calendaring and tamper detect registers.
BCD format enable. This bit controls whether the read/write value of time and date registers will be in
binary or BCD. The registers are maintained in binary and the conversion to BCD to binary or vice-versa
is done for the read/write IPS bus. It is done for some registers only.
‘1’ – Registers read for Hour, Minutes, Seconds and Day displayed in BCD format
‘0’ – Registers read for Hour, Minutes, Seconds and Day displayed in Binary format
BCDEN
OCLK
Bit 15
Bit 7
rw
rw
1
0
DSTEN
Figure 17-10. IRTC Control Register (IRTC_CTRL)
Bit 14
OFF_CHIP_CLK
Bit 6
rw
rw
0
0
Table 17-10. IRTC_CTRL Field Descriptions
Bit 13
rsvd
Bit 5
rw
—
0
IRTC Control Register
Bit 12
rsvd
Bit 4
rw
—
0
TAMPER DETECT DURATION
Description
Bit 11
ALARM MATCH
Bit 3
rw
rw
0
0
Bit 10
Bit 2
rw
rw
0
0
rw/sclr
WE1
Bit 9
Bit 1
rw
0
0
Freescale Semiconductor
rw/sclr
rw/sclr
SWR
WE0
Bit 8
Bit 0
Offset: 0x10
0
0
0x10
0x11