MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 574

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF51EM256CLL
Manufacturer:
FREESCALE
Quantity:
110
Part Number:
MCF51EM256CLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Version 1 ColdFire Debug (CF1_DEBUG)
26.3.2
The 32-bit XCSR is partitioned into two sections: the upper byte contains status and command bits always
accessible to the BDM interface, even if debug mode is disabled. This status byte is also known as
XCSR_SB. The lower 24 bits contain fields related to the generation of automatic SYNC_PC commands,
which can be used to periodically capture and display the current program counter (PC) in the PST trace
buffer (if properly configured).
There are multiple ways to reference the XCSR. They are summarized in
26-10
Field
SSM
DDH
3–2
FID
IPI
5
4
1
0
WRITE_XCSR_BYTE Writes XCSR[31
WDEBUG instruction Writes XCSR[23
READ_XCSR_BYTE Reads XCSR[31
WRITE_DREG
READ_DREG
Method
Ignore pending interrupts when in single-step mode.
0 Core services any pending interrupt requests signalled while in single-step mode.
1 Core ignores any pending interrupt requests signalled while in single-step mode.
Single-step mode enable.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command
Reserved, must be cleared.
Force ipg_debug. The core generates this output to the device, signaling it is in debug mode.
0 Do not force the assertion of ipg_debug
1 Force the assertion of ipg_debug
Disable ipg_debug due to a halt condition. The core generates an output to the other modules in the device,
signaling it is in debug mode. By default, this output signal is asserted when the core halts.
0 Assert ipg_debug if the core is halted
1 Negate ipg_debug due to the core being halted
Extended Configuration/Status Register (XCSR)
can be executed. On receipt of the GO command, the processor executes the next instruction and halts again.
This process continues until SSM is cleared.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Reads XCSR[31
Writes XCSR[23
is a privileged supervisor-mode instruction.
Table 26-5. CSR Field Descriptions (continued)
Table 26-6. XCSR Reference Summary
24] from the BDM interface. Available in all modes.
0] from the BDM interface. Classified as a non-intrusive BDM command.
0] from the BDM interface. Classified as a non-intrusive BDM command.
0] during the core’s execution of WDEBUG instruction. This instruction
24] from the BDM interface. Available in all modes.
Description
Reference Details
Table
26-6.
Freescale Semiconductor

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