MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 117

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2.2.4
The pad cells on this device incorporate optional low pass filters on the digital input functions. These are
enabled by setting the appropriate bit in the input filter enable register (PTxIFE[n]). When set, a low pass
filter (10 MHz to 30 MHz bandwidth) is enabled in the logic input path. When cleared, the filter is
bypassed.
4.3
4.3.1
Reading and writing of parallel I/Os are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in
The data direction control bit (PTxDD[n]) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
GPIO equipped with set/clear/toggle support single CPU instruction commands for set, clear and toggle
of a GPIO output level. Set/clear/toggle functions are not present on all V1 ColdFire I/O ports. See the
summary table earlier in this chapter for capabilities of your specific device.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit continues to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, the input and output buffers are disabled. A value of
0 is read for any port data bit where the bit is an input (PTxDD[n] = 0) and the input buffer is disabled.
Writing to the port data register before changing the direction of a port pin to an output ensures that the pin
is not driven momentarily with an old data value in the port data register.
Freescale Semiconductor
Reset:
PTxIFEn
Field
•
•
•
7–0
W
R
Writing a one to a bit of any PTxSET register sets that output function to logic one.
Writing a one to the PTxCLR register sets the output function to zero.
Writing a one to the PTxTOG register toggles the output value.
Standard GPIO and GPIO Equipped with Set/Clear/Toggle
PTxIFE7
GPIO Overview
Port x Input Filter Enable — Input low-pass filter enable control bits for PTx pins.
0 Input filter disabled
1 Input filter enabled
Port x Input Filter Enable Register (PTxIFE)
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
PTxIFE6
0
Figure 4-5. Port x Input Filter Enable Register (PTxIFE)
6
Table 4-10. PTxIFE Field Descriptions
PTxIFE5
0
5
PTxIFE4
0
4
Description
Figure
PTxIFE3
3
0
4-6.
PTxIFE2
0
2
PTxIFE1
0
1
PTxIFE0
0
0
4-7