MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 360

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (IIC)
Note: In Master receive mode the FACK should be set zero before the last byte transfer.
15.6.1
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion
of byte transfer.
15.6.2
When the calling address matches the programmed slave address (IIC address register) or when the
GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is
interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
15.6.3
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
This bit must be cleared by software by writing a 1 to it.
15.6.4
When IICIE is set, the IIC asserts a timeout interrupt output SLTF upon detection of any of the mentioned
timeout conditions, with one exception. The HIGH TIMEOUT mechanism shall not be used to influence
the timeout interrupt output, because the HIGH TIMEOUT indicates an idle condition on the bus.
15-22
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SDA sampled as a low when the master drives a high during an address or data transmit cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
A START cycle is attempted when the bus is busy.
A repeated START cycle is requested in slave mode.
A STOP condition is detected when the master did not request it.
Byte Transfer Interrupt
Address Detect Interrupt
Arbitration Lost Interrupt
Timeouts Interrupt in SMbus
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Match of received calling address
SMBus Timeout Interrupt Flag
Complete 1-byte transfer
Interrupt Source
Arbitration Lost
Table 15-16. Interrupt Summary
Status
ARBL
SLTF
IAAS
TCF
IICIF
IICIF
IICIF
IICIF
Flag
Local Enable
IICIE
IICIE
IICIE
IICIE
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