MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 630

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
Table 26-28
26.4.3.4.2
The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown
below. The PST/DDATA specification for these opcodes is shown in
26-66
2
halt
move.l
move.l
move.w
move.w
movec.l
Instruction
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address
fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi),
(d8,PC,Xi).
mac.l
mac.l
mac.w
mac.w
move.l
move.l
move.l
move.l
move.l
move.l
move.l
msac.l
msac.l
msac.w
msac.w
Instruction
shows the PST/DDATA specification for the MAC instructions.
Supervisor Instruction Set
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 26-29. PST/DDATA Specification for Supervisor-Mode Instructions
Ay,USP
USP,Ax
SR,Dx
{Dy,#<data>},SR
Ry,Rc
Operand Syntax
Table 26-28. PST/DDATA Values for Multiply-Accumulate Instructions
Ry,Rx
Ry,Rx,<ea>y,Rw
Ry,Rx
Ry,Rx,ea,Rw
{Ry,#<data>},ACC
{Ry,#<data>},MACSR
{Ry,#<data>},MASK
ACC,Rx
MACSR,CCR
MACSR,Rx
MASK,Rx
Ry,Rx
Ry,Rx,<ea>y,Rw
Ry,Rx
Ry,Rx,<ea>y,Rw
Operand Syntax
PST = 0x1F,
PST = 0x1F
PST = 0x01
PST = 0x01
PST = 0x01
PST = 0x01, {PST = 0x03}
PST = 0x01
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source},
{PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source},
{PST = 0xB, DD = destination}
PST/DDATA
PST/DDATA
Table
26-29.
Freescale Semiconductor