MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 486

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC16)
21.5.5.5
The total conversion time depends upon: the sample time (as determined by ADLSMP and ADLSTS bits),
the MCU bus frequency, the conversion mode (as determined by MODE and DIFFn bits), the high speed
configuration (ADHSC bit), and the frequency of the conversion clock (
The ADHSC bit is used to configure a higher clock input frequency. This will allow faster overall
conversion times. In order to meet internal A/D converter timing requirements the ADHSC bit adds
additional ADCK cycles. Conversions with ADHSC = 1 take four more ADCK cycles. ADHSC should be
used when the ADCLK exceeds the limit for ADHSC = 0.
After the module becomes active, sampling of the input begins. ADLSMP and ADLSTS select between
sample times based on the conversion mode that is selected. When sampling is complete, the converter is
isolated from the input channel and a successive approximation algorithm is performed to determine the
digital value of the analog signal. The result of the conversion is transferred to ADCRHn and ADCRLn
upon completion of the conversion algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). The maximum total conversion time
is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by
the ADICLK bits, and the divide ratio is specified by the ADIV bits. The maximum total conversion time
for all configurations is summarized in the equation below. Refer to
the variables referenced in the equation.
21-30
ConversionTime
Sample Time and Total Conversion Time
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 21-17. Single or First Continuous Time Adder (SFCAdder)
1
1
1
1
0
0
0
ADACKEN must be 1 for at least 5us prior to the conversion is initiated
to achieve this time
=
x
1
0
x
1
0
SFCAdder
0x, 10
0x, 10
Conversion Time Equation
11
11
11
11
ADCK
+
frequency, precise sample time for continuous conversions
AverageNum
Single or First Continuous Time Adder
5μs + 3 ADCK cycles + 5 bus clock cycles
5μs + 5 ADCK cycles + 5 bus clock cycles
3 ADCK cycles + 5 bus clock cycles
5 ADCK cycles + 5 bus clock cycles
3 ADCK cycles + 5 bus clock cycles
5 ADCK cycles + 5 bus clock cycles
(SFCAdder)
×
(
BCT
+
Table 21-17
LSTAdder
f
ADCK
).
1
1
through
+
HSCAdder
Freescale Semiconductor
Table 21-21
)
Eqn. 21-1
for