MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 389

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Independent Robust Real Time Clock (IRTC)
A countdown timer with minute resolution is also provided for time keeping applications. This counter can
be enabled or disabled separately. An interrupt is generated at the expiry of the counter. IRTC module also
provides seven sampling timer interrupts apart from normal interrupts for alarm and countdown timeout.
A frequency compensation module is integrated into the IRTC to correct any error in 1 Hz clock due to
variations in the 32 kHz clock caused by crystal inaccuracy, board variations or change in temperature. The
compensation value for both crystal and temperature variation is set by software and correction is done in
hardware.
The registers in the IRTC are programmable via the IPS bus. A protection mechanism is built-in the IRTC
to protect against spurious writes into the IRTC by any run-away code. The protection mechanism requires
the CPU to write a specific sequence of codes to the IRTC_CTRL[1:0] bits in the control register that
allows write access to the registers. On completing the update of registers the CPU writes any value to
IRTC_CTRL[1:0] bits to enable the write protection. After unlocking the registers, the CPU has a window
of two seconds for updating the register space. On power on reset a window of 15 seconds is allowed for
the CPU to configure the IRTC after which the registers are locked. Any further updates would require the
CPU to unlock the registers.
The IRTC battery supply maintains normal RTC functionality when the CPU power is removed. The
battery supply allows IRTC to keep functioning in case CPU is completely turned off. Reset to the IRTC
block is generated only when both battery supply and CPU power are removed and either is powered up.
The reset generation and switching of power is done external to the IRTC by an analog switch/regulator.
The IRTC is also equipped with a RAM that will be powered by the battery supply in the event of main
supply being switched off. The size of this memory is 32 bytes. MCU can use this RAM to store any data
it wants to retain in case the MCU power is switched off. This RAM will loose all its contents when both
MCU and battery power have been removed.
IRTC can detect any intrusion via its tamper detection mechanism that will get enabled automatically after
the calibration of IRTC is complete. For this purpose, a pin has been provided and high level input on this
pin indicates a tamper which will get stored in the IRTC registers. Removal of battery after calibration will
also be indicated as a tamper. Any tamper detected will cause an interrupt to the CPU. IRTC can also store
the time and date stamp of the latest tamper event recorded. Tamper detection and its interrupt are enabled
on reset.
IRTC has a 32-bit up-counter register that keeps incrementing on writes and read to this register returns
the latest count value. This register will be of use in metering kind of applications where this register can
be used to store the energy consumed over a period of time.
Figure 17-1
shows the block diagram for IRTC.
17.5
IRTC Programming Model
The IRTC contains twenty four 16-bit aligned registers and standby RAM. The table below summarized
the registers and their address with access type. Both the registers and the standby RAM can be accessed
via 8-bit and 16-bit read/write cycles.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor
17-5