MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 611

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.4.1.5.15 READ_CSR2_BYTE
Read the most significant byte of CSR2 (CSR2[31–24]). This command can be executed in any mode.
26.4.1.5.16 READ_CSR3_BYTE
Read the most significant byte of the CSR3 (CSR3[31–24]). This command can be executed in any mode.
26.4.1.5.17 SYNC_PC
Capture the processor’s current PC (program counter) and display it on the PST/DDATA signals. After the
debug module receives the command, it sends a signal to the ColdFire core that the current PC must be
displayed. The core responds by forcing an instruction fetch to the next PC with the address being captured
by the DDATA logic. The DDATA logic captures a 2- or 3-byte instruction address, based on CSR[9]. If
CSR[9] is cleared, then a 2-byte address is captured, else a 3-byte address is captured. The specific
sequence of PST and DDATA values is defined as:
This command can be used to provide a PC synchronization point between the core’s execution and the
application code in the PST trace buffer. It can also be used to dynamically access the PC for performance
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1. Debug signals a SYNC_PC command is pending.
2. CPU completes the current instruction.
3. CPU forces an instruction fetch to the next PC, generating a PST = 0x5 value indicating a taken
branch. DDATA captures the instruction address corresponding to the PC. DDATA generates a PST
marker signalling a 2- or 3-byte address as defined by CSR[9] (CSR[9] = 0, 2-byte; CSR[9] = 1,
3-byte) and displays the captured PC address.
Read CSR2 Status Byte
Read CSR3 Status Byte
Synchronize PC to PST/DDATA Signals
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
host →
host →
host →
target
target
target
0x2E
0x2F
0x01
D
L
Y
target →
target →
[31–24]
[31–24]
CSR2
CSR3
host
host
Version 1 ColdFire Debug (CF1_DEBUG)
Always Available
Always Available
Non-intrusive
26-47