MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 279

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NOTE
Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These
changes should be performed as separate operations or unexpected behavior may occur.
12.4.2
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
Freescale Semiconductor
Reset
LSBFE
MSTR
CPHA
SSOE
CPOL
Field
4
3
2
1
0
W
R
SPI Control Register 2 (SPIxC2)
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
MODFEN
0
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
0
1
1
= Unimplemented or Reserved
0
0
6
Section 12.5.1, “SPI Clock
SSOE
Table 12-1. SPIxC1 Field Descriptions (continued)
0
1
0
1
Figure 12-5. SPI Control Register 2 (SPIxC2)
Section 12.5.1, “SPI Clock
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
0
0
5
Table 12-2. SS Pin Function
MODFEN
Master Mode
Formats”
0
4
Description
Formats”
for more details.
BIDIROE
3
0
for more details.
Slave select input
Slave select input
Slave select input
Slave select input
0
0
2
8-bit Serial Peripheral Interface (SPI)
Slave Mode
SPISWAI
0
1
Table
SPC0
0
0
12-2.
12-7