MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 495

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.6.1
21.6.1.1
Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
21.6.1.2
In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion
at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from
the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
ADCSC2 = 0x00 (%00000000)
ADCSC1A = 0x41 (%01000001)
ADCRHA/LA = 0xxx
Freescale Semiconductor
1. Calibrate the ADC by following the calibration instructions in
2. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
3. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
4. Update status and control register 3 (ADSC3) to select whether conversions will be continuous or
5. Update status and control register (ADCSC1:ADCSC1n) to select whether conversions will be
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
software) and compare function options, if enabled.
completed only once (ADCO) and to select whether to perform hardware averaging.
single-ended or differential and to enable or disable conversion complete interrupts. The input
channel on which conversions will be performed is also selected here.
Bit 7
Bit 6:5 ADIV
Bit 4
Bit 3:2 MODE
Bit 1:0 ADICLK
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:2
Bit 1:0
Bit 7
Bit 6
Bit 5
Bit 4:0 ADCHA
Holds results of conversion. Read high byte (ADCRHA) before low byte (ADCRLA) so that
conversion data cannot be overwritten with data from the next conversion.
ADC Module Initialization Example
Initialization Sequence
Pseudo-Code Example
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
ADLPC
ADLSMP
ADACT
ADTRG
ACFE
ACFGT
COCOA
AIENA
ADCOA
1
00
1
10
00
0
0
0
0
00
00
0
1
0
00001
Configures for low power (lowers maximum clock speed.
Sets the ADCK to the input clock ÷ 1.
Configures for long sample time.
Sets mode at 10-bit conversions.
Selects bus clock as input clock source.
Flag indicates if a conversion is in progress.
Software trigger selected.
Compare function disabled.
Not used in this example.
Reserved, always reads zero.
Reserved for Freescale’s internal use; always write zero.
Read-only flag which is set when a conversion completes.
Conversion complete interrupt enabled.
One conversion only (continuous conversions disabled).
Input channel 1 selected as ADC input channel.
Section
Analog-to-Digital Converter (S08ADC16)
21.5.7.
21-39