MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 566

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.1.1
Debug support is divided into three areas:
26-2
•
•
Background debug mode (BDM)—Provides low-level debugging in the ColdFire processor core.
In BDM, the processor core is halted and a variety of commands can be sent to the processor to
access memory, registers, and peripherals. The external emulator uses a one-pin serial
communication protocol. See
Real-time debug support—Use of the full BDM command set requires the processor to be halted,
which many real-time embedded applications cannot support. The core includes a variety of
internal breakpoint registers which can be configured to trigger and generate a special interrupt.
The resulting debug interrupt lets real-time systems execute a unique service routine that can
quickly save the contents of key registers and variables and return the system to normal operation.
The external development system can then access the saved data, because the hardware supports
IPL_B[2:0]
RESET
Overview
BKGD
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-1. Simplified Version 1 ColdFire Core Block Diagram
Version 1 ColdFire Core (CF1Core)
IFP
OEP
BDC
CFxBDM
PST/DDATA — Processor status/debug data
RTD
Central Processing Unit
(CF1Cpu)
Debug
(CF1Dbg)
BDC
Section 26.4.1, “Background Debug Mode (BDM)”.
— Instruction fetch pipeline
— Operand execution pipeline
— Background debug controller
— ColdFire background debug module
— Real-time debug
BDM
CFx
OEP
DDATA
IFP
RTD
PST/
Freescale Semiconductor
wdata
addr
rdata
attb