MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 499

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.7.2.3
System noise that occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
21.7.2.4
The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or
12), defined as 1
There is an inherent quantization error due to the digitalization of the result. For 8-bit or 10-bit conversions
the code transitions when the voltage is at the midpoint between the points where the straight line transfer
function is exactly represented by the actual transfer function. Therefore, the quantization error will be ±
1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the first (0x000) conversion is
only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.
Freescale Semiconductor
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There is a 0.1 μF low-ESR capacitor from V
There is a 0.1 μF low-ESR capacitor from V
If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
V
V
Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to ADCSC1 with a wait
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V
There is no I/O switching, input or output, on the MCU during the conversion.
Place a 0.01 μF capacitor (C
noise issues, but affects the sample rate based on the external analog source resistance).
Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1
Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
DDAD
SSAD
instruction or stop instruction.
noise but increases effective conversion time due to stop recovery.
DD
Noise-Induced Errors
Code Width and Quantization Error
(and V
noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
to V
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
LSB
SSAD
, is:
REFL
.
, if connected) is connected to V
1 lsb = (V
AS
) on the selected input channel to V
REFH
- V
REFL
REFH
DDAD
) / 2
to V
to V
SS
N
at a quiet point in the ground plane.
REFL
SSAD
.
.
Analog-to-Digital Converter (S08ADC16)
REFL
LSB
or V
, one-time error.
SSAD
(this improves
Eqn. 21-3
21-43
DD