MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 529

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LCDBPEN0
LCDBPEN1
LCDBPEN2
LCDBPEN3
LCDBPEN4
LCDBPEN5
Read: anytime
Write: anytime
24.3.9
Each frontplane segment is associated with a backplane phase (A-H). For an LCD pin configured as a
frontplante the LCDWF registers control the on/off state for frontplane segments.
For an LCD pin configured as a backplane the LCDWF registers controls the phase (A-H) in which the
associated backplane pin is active.
These registers should only be written with instructions that perform byte writes, using instructions that
perform word writes will lead to invalid data being placed in the register.
After reset, the LCDWF contents are indeterminate as indicated by
not require reinitializing the LCDWF registers.
Freescale Semiconductor
BPEN[43:0]
Field
Reset
Reset
Reset
Reset
Reset
Reset
LCD Waveform Registers (LCDWF[43:0])
W
W
W
W
W
W
R
R
R
R
R
R
Backplane Enable — The BPEN[43:0] bit configures the LCD[43:0] pin to operate as an LCD backplane or LCD
frontplane. If LCDEN = 0, these bits have no effect on the state of the I/O pins. It is recommended to set
BPEN[63:0] bits before LCDEN is set.
0 Frontplane operation enabled on LCD[n].
1 Backplane operation enabled on LCD[n].
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
BPEN15
BPEN23
BPEN31
BPEN39
BPEN7
Figure 24-9. Backplane Enable Registers 0–7 (BPEN0–BPEN7)
7
Table 24-12. LCDBPEN0–LCDBPEN Field Descriptions
BPEN14
BPEN22
BPEN30
BPEN38
BPEN6
Unimplemented or Reserved
6
BPEN13
BPEN21
BPEN29
BPEN37
BPEN5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
BPEN12
BPEN20
BPEN28
BPEN36
BPEN4
Description
4
BPEN11
BPEN19
BPEN27
BPEN35
BPEN43
BPEN3
Figure
3
24-10. Exiting stop2 mode does
BPEN10
BPEN18
BPEN26
BPEN34
BPEN42
BPEN2
2
BPEN17
BPEN25
BPEN33
BPEN41
BPEN1
BPEN9
1
LCD Driver Module
BPEN16
BPEN24
BPEN32
BPEN40
BPEN0
BPEN8
24-13
0