MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 207

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.3.3.3
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
illegal instruction is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is
generated as detailed below. There is one special case involving the ILLEGAL opcode (0x4AFC)
attempted execution of this instruction always generates an illegal instruction exception, regardless of the
state of the CPUCR[IRD] bit.
The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See
definition is shown in
Freescale Semiconductor
Opword[Line]
15
0xC
0xD
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xE
0xF
14
Illegal Instruction Exception
Line
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Move Byte
Move Word
Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)
Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)
Logical OR (OR)
Bit manipulation, Arithmetic and Logical Immediate
Move Long
Miscellaneous
PC-relative change-of-flow instructions
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)
Subtract (SUB), Subtract Extended (SUBX)
MAC, Move 3-bit Quick (MOV3Q)
Compare (CMP), Exclusive-OR (EOR)
Logical AND (AND), Multiply Word (MUL)
Add (ADD), Add Extended (ADDX)
Arithmetic and logical shifts (ASL, ASR, LSL, LSR)
Write DDATA (WDDATA), Write Debug (WDEBUG)
13
Figure 8-11. ColdFire Instruction Operation Word (Opword) Format
Table
12
8-9.
11
Table 8-9. ColdFire Opword Line Definition
10
OpMode
9
8
Instruction Class
7
6
5
Figure
Mode
4
8-11. The opword line
Effective Address
3
2
Register
1
ColdFire Core
;
0
8-15