MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 573

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
12–11
Field
DDC
BKD
TRC
UHE
BTB
NPL
IPW
9–8
18
17
16
15
14
13
10
7
6
Breakpoint disable. Disables the BACKGROUND command functionality, and allows the execution of the
BACKGROUND command to generate a debug interrupt.
0 Normal operation
1 The receipt of a BDM BACKGROUND command signals a debug interrupt to the ColdFire core. The processor
Reserved, must be cleared.
Inhibit processor writes. Inhibits processor-initiated writes to the debug module’s programming model registers.
IPW can be modified only by commands from the BDM interface.
Reserved, must be cleared.
Force emulation mode on trace exception.
0 Processor enters supervisor mode.
1 Processor enters emulator mode when a trace exception occurs.
Reserved, must be cleared.
Debug data control. Controls peripheral bus operand data capture for DDATA, which displays the number of bytes
defined by the operand reference size (a marker) before the actual data; byte displays 8 bits, word displays 16
bits, and long displays 32 bits (one nibble at a time across multiple PSTCLK clock cycles). See
non-zero value enables partial data trace capabilities.
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
User halt enable. Selects the CPU privilege level required to execute the HALT instruction. The core must be
operating with XCSR[ENBDM] set to execute any HALT instruction, else the instruction is treated as an illegal
opcode.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
Branch target bytes. Defines the number of bytes of branch target address DDATA displays. See
“Begin Execution of Taken Branch (PST = 0x05).”
00 No target address capture
01 Lower 2 bytes of the target address
1x Lower 3 bytes of the target address
Reserved, must be cleared.
Non-pipelined mode. Determines if the core operates in pipelined mode.
0 Pipelined mode
1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap. This typically
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction
executes. In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is imprecise.
In non-pipeline mode, these triggers are always reported before the next instruction begins execution and trigger
reporting can be considered precise.
makes this interrupt request pending until the next sample point occurs, when the exception is initiated. In the
ColdFire architecture, the interrupt sample point occurs once per instruction. There is no support for nesting
debug interrupts.
adds five cycles to the execution time of each instruction. Given an average execution latency of ~2 cycles per
instruction, throughput in non-pipeline mode would be ~7 cycles per instruction, approximately 25% - 33% of
pipelined performance.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 26-5. CSR Field Descriptions (continued)
Description
Version 1 ColdFire Debug (CF1_DEBUG)
Section 26.4.3.1,
Table
26-26. A
26-9