MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 155

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
Run mode — processor and peripherals
clocked normally.
LPrun mode with low voltage detect
disabled — processor and peripherals
clocked at low frequency
Low voltage detects are not active.
Wait mode — processor clock nominally
inactive, but peripherals are clocked.
LPwait mode — processor clock is
inactive, peripherals are clocked at low
frequency and the PMC is loosely
regulating.
Low voltage detects are not active.
Stop modes disabled — Illegal opcode
reset if STOP instruction executed and
CPUCR[IRD] is cleared, else illegal
instruction exception is generated.
Stop4 — Either low-power modes have
not been requested, or low voltage
detects are enabled or
XCSR[ENBDM] = 1.
Stop3 — Low voltage detect in stop is
not enabled. Clocks must be at low
frequency and are gated. The regulator
is in loose regulation.
Stop2 — Low voltage detects are not
active. If BDC is enabled, stop4 is
invoked rather than stop2.
Freescale Semiconductor
ENBDM is located in the upper byte of the XCSR register which is write-accessible only through BDC commands, see
Section 26.3.2, “Extended Configuration/Status Register (XCSR)”.
250 kHz maximum CPU frequency in LPrun; 125 kHz maximum peripheral clock frequency.
Assuming that neither low voltage interrupts nor BDM are enabled, stop3 can be entered from run simply by executing a STOP
command. It can also be entered from LPrun via stop.
Mode of Operation
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
2
.
Table 6-1. CPU / Power Mode Selections
SOPT1
x
x
x
x
0
1
1
1
SIM
1
1
0
0
0
0
x
x
of BKGD/
Function
XCSR
BDC
MS at
reset
x
x
1
0
0
x
x
1
0
x
x
x
1
0
0
SPMSC1
⇒
1
0
1
1
0
1
1
1
1
0
0
x
x
x
x
x
x
x
PMC
1
⇒
x
1
x
x
0
x
1
x
x
0
1
1
1
x
0
x
0
x
1
SPMSC2
⇒
X
0
x
x
1
0
x
x
1
0
1
0
x
0
3
PMC
0
⇒
x
x
x
0
x
x
x
0
0
0
1
x
0
1
0
off. CPU clock on if
XCSR[ENBDM]=1
XCSR[ENBDM]=1
Low freq required.
Peripheral clocks
Peripheral clocks
Peripheral clocks
Periph clocks off.
peripheral clocks
CPU clock is off.
mode. CPU and
required. ICS in
CPU clock on if
On. ICS in any
Low frequency
Peripheral
CPU clock on.
FBELP mode.
at low speed.
ICS in BLPE.
are gated off.
ICS in BLPE
CPU and
Clocks
⇒
mode
N/A
On
on
On
clock can be gated
off at the discretion
that negative edge
BKGD/MS at reset
BDC clock enabled
XCSR[ENBDM]=1
needed, the BDC
available within a
BKGD. The BDM
of the processor.
Effects on Sub-System
normally when a
negative edge is
Note: When not
prior to entering
associated with
BDC Clock
demand by the
few cycles of
may not take
The clock is
detected on
Function of
processor,
command
affect.
only if
stop.
N/A
Modes of Operation
On
Off
Switched
Loose Reg
Loose Reg
Loose Reg
Power
⇒
On
On
On
Off
On
6-3