MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 251

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Level
10.4
The basic operation of the CF1_INTC is detailed in the preceding sections. This section describes special
rules applicable to non-maskable level seven interrupt requests and the module’s interfaces.
10.4.1
The CPU treats level seven interrupts as non-maskable, edge-sensitive requests, while levels one through
six are maskable, level-sensitive requests. As a result of this definition, level seven interrupt requests are
a special case. The edge-sensitive nature of these requests means the encoded 3-bit level input from the
CF1_INTC to the V1 ColdFire core must change state before the CPU detects an interrupt. A
non-maskable interrupt (NMI) is generated each time the encoded interrupt level changes to level seven
(regardless of the SR[I] field) and each time the SR[I] mask changes from seven to a lower value while the
encoded request level remains at seven.
10.5
The reset state of the CF1_INTC module enables the default IRQ mappings and clears any software-forced
interrupt requests (INTC_FRC is cleared). Immediately after reset, the CF1_INTC begins its
cycle-by-cycle evaluation of any asserted interrupt requests and forms the appropriate encoded interrupt
level and vector information for the V1 Coldfire processor core. The ability to mask individual interrupt
requests using the interrupt controller’s IMR is always available, regardless of the level of a particular
interrupt request.
10.6
This section discusses three application topics: emulation of the HCS08’s one level interrupt nesting
structure, elevating the priority of two IRQs, and more details on the operation of the software interrupt
acknowledge (SWIACK) mechanism.
Freescale Semiconductor
3
2
1
Table 10-12. ColdFire [Level][Priority within Level] Matrix Interrupt Assignments (continued)
23
SCI2_err
Functional Description
Initialization Information
Application Information
—
—
7
Handling of Non-Maskable Level 7 Interrupt Requests
87
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
24
31
38
SCI2_rx
IRTC
IIC
6
102
88
95
25
32
39
SCI2_tx
CMP1
LCD
5
110
89
96
26
33
SCI3_err
CMP2
—
4
Priority within Level
90
97
Midpoint
—
—
—
27
41
SCI3_rx
FTSR1
—
3
112
91
28
35
42
SCI3_tx
FTSR2
KBI1
2
113
92
99
Interrupt Controller (CF1_INTC)
36
KBI2
—
—
1
100
FRC[60]
FRC[61]
FRC[62]
force_lvl3
force_lvl1
force_lvl2
0
10-15
107
108
109