MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 157

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 6-2
Freescale Semiconductor
Transition #
defines triggers for various state transitions shown in
1
2
3
4
5
6
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 6-3. All Allowable Power Mode Transitions for MCF51EM256 Series
Halt
LPwait
LPwait
LPrun
LPrun
LPrun
Stop2
Stop3
Stop4
From
11
Wait
Run
Run
Run
Run
Run
9
Table 6-2. Triggers for State Transition
10
Stop4
Wait
7
6
Run
LPwait
LPwait
LPrun
Stop2
LPrun
Stop3
LPrun
Stop4
Wait
Run
Run
Run
Run
Run
To
8
5
2
LPwait
Stop3
Stop2
Configure settings shown in
LPR = 1 last
Clear SPMSC2[LPR]
Interrupt when SPMSC2[LPWUI] = 1
Negative transition on enabled BKGD/MS pin.
Pre-configure settings shown in
STOP instruction
Assert zero on RESET
environment from RAM. IRQ assertion
Pre-configure settings shown in
STOP instruction
Interrupt when SPMSC2[LPWUI]=0
Execute STOP instruction
Interrupt when SPMSC2[LPWUI]=0
Interrupt when SPMSC2[LPWUI]=1
Not supported.
Pre-configure settings shown in
STOP instruction
Interrupt
Pre-configure settings shown in
STOP instruction
Interrupt
1
Figure
6-2.
3
4
LPrun
Trigger
1
or IRTC timeout. Reload
Table
Table
Table
Table
Table
6-1, switch
Modes of Operation
6-1, execute
6-1, execute
6-1, execute
6-1, execute
6-5