MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 103

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4.6
3.4.6.1
The FACCERR flag will be set during the command write sequence if any of the following illegal steps
are performed, causing the command write sequence to immediately abort:
The FACCERR flag will also be set if the MCU enters stop mode while any command is active (FCCF=0).
The operation is aborted immediately and, if burst programming, any pending burst program command is
purged (see
The FACCERR flag will not be set if any flash register is read during a valid command write sequence.
If the flash memory is read during execution of an algorithm (FCCF = 0), the read operation will return
invalid data and the FACCERR flag will not be set.
If the FACCERR flag is set in the FxSTAT register, the user must clear the FACCERR flag before starting
another command write sequence (see
3.4.6.2
The FPVIOL flag will be set after the command is written to the FxCMD register during a command write
sequence if any of the following illegal operations are attempted, causing the command write sequence to
immediately abort:
Freescale Semiconductor
1. Writing to a flash address before initializing the FxCDIV register.
2. Writing a byte, word, or misaligned longword to a valid flash address.
3. Writing to any flash register other than FxCMD after writing to a flash address.
4. Writing to a second flash address in the same command write sequence.
5. Writing an invalid command to the FxCMD register unless the address written was in a protected
6. Writing a command other than burst program while FCBEF is set and FCCF is clear.
7. When security is enabled, writing a command other than erase verify or mass erase to the FxCMD
8. Writing to a flash address after writing to the FxCMD register.
9. Writing to any flash register other than FxSTAT (to clear FCBEF) after writing to the FxCMD
10. Writing a 0 to the FCBEF flag in the FxSTAT register to abort a command write sequence.
1. Writing the program command if the address written in the command write sequence was in a
2. Writing the sector erase command if the address written in the command write sequence was in a
3. Writing the mass erase command while any flash protection is enabled.
area of the flash array.
register when the write originates from a non-secure memory location or from the background
debug mode.
register.
protected area of the flash array.
protected area of the flash array.
Illegal Flash Operations
Section 3.4.7.2, “Stop
Flash Access Violations
Flash Protection Violations
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Mode”).
Section 3.4.3.5, “Flash Status Register
(FxSTAT)”).
Memory
3-47