MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 161

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.8
One of three stop modes is entered upon execution of a STOP instruction when SOPT1[STOPE] is set. The
SOPT1[WAITE] bit must be clear, else wait mode is entered. In stop3 mode, the bus and CPU clocks are
halted. If XCSR[ENBDM] is set prior to entering stop4, only the peripheral clocks are halted. The ICS
module can be configured to leave the reference clocks running. See
(ICS),”
The stop modes are selected by setting the appropriate bits in the system power management status and
control 2 (SPMSC2) register.
various conditions. The selected mode is entered following the execution of a STOP instruction.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop4 and enter halt mode if
XCSR[ENBDM] was set prior to entering stop. After entering halt mode, all background commands are
available.
6.8.1
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in
Most of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM and the
IRTC. Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during
stop2.
Exit from stop2 is performed by driving the wake-up pin (RESET and PTA0/RGPIO0/IRQ/CLKOUT) on
the MCU to zero.
In addition, the independent real-time counter (IRTC) can wake the MCU from stop2, if enabled.
Upon wakeup from stop2 mode, the MCU starts up as from a power-on reset (POR):
Freescale Semiconductor
•
All module control and status registers are reset, with the exception of the power management
controller (SPMSC1/2/3), IRTC, LCD, and debug trace buffer. Refer to the individual module
chapters for more information on which other registers are unaffected by wake-up from stop2
mode.
for more information.
Stop Modes
Stop2 Mode
If neither the WAITE nor STOPE bit is set when the CPU executes a STOP
instruction, the MCU does not enter either of the stop modes. Instead, the
MCU initiates an illegal opcode reset if CPUCR[IRD] is cleared or an
illegal instruction exception if CPUCR[IRD] is set.
PTA0/RGPIO0/IRQ/CLKOUT functions as an active-low wakeup input
when the MCU is in stop2, as long as the pin is configured as an input before
entering stop2. The pullup on this pin is not automatically enabled in stop2.
To enable the internal pullup, set PTAPE[PTAPE0].
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 6-1
shows all of the control bits that affect mode selection under
NOTE
NOTE
Chapter 11, “Internal Clock Source
Modes of Operation
Table
6-1.
6-9