MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 168

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets, Interrupts, and General System Control
7.3.1
When the microcontroller is in stop2 mode and system clocks are shut down, a separate asynchronous path
from RESETB to the PMC can be used to wake the device from stop2.
7.3.2
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to an known starting point.
After any reset, the COP watchdog is enabled (see
for additional information). If the COP watchdog is not used in an application, it can be disabled by
clearing SOPT1[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the
selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence
is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the
microcontroller will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the
microcontroller is immediately reset.
The SOPT1[COPCLKS] field selects the clock source used for the COP timer. The clock source options
are either the bus clock or an internal 1 kHz clock source. With each clock source, there are three
associated time-outs controlled by SOPT1[COPT].
COPCLKS and COPT bits. The COP watchdog defaults to operation from the 1 kHz clock source and the
longest time-out (2
When the bus clock source is selected, windowed COP operation is available by setting SOPT1[COPW].
In this mode, writes to the SRS register to clear the COP timer must occur in the last 25% of the selected
timeout period. A premature write immediately resets the microcontroller. When the 1 kHz clock source
is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SOPT1 register and after any system reset.
Subsequent writes to SOPT1 have no effect on COP operation. Even if the application will use the reset
default settings of the COPT, COPCLKS, and COPW bits, the user should write to the write-once SOPT1
register during reset initialization to lock in the settings. This will prevent accidental changes if the
application program gets lost.
7-2
RESETB
Computer Operating Properly (COP) Watchdog
This pin does not contain a clamp diode to V
above V
The voltage measured on the internally pulled up RESET pin will not be
pulled to V
The RESET pullup must not be used to pull up components external to the
microcontroller.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
10
cycles).
DD
DD
.
. The internal gates connected to this pin are pulled to V
NOTE
NOTE
Section 7.7.6, “System Options 1 (SOPT1) Register,”
Table 7-10
DD
summarizes the control functions of the
and must not be driven
Freescale Semiconductor
DD
.