MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 159

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.6
6.6.1
Run mode is the normal operating mode for the MCF51EM256 series. This mode is selected when the
BKGD/MS pin is high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches
the supervisor SR and initial PC from locations 0x(00)00_0000 and 0x(00)00_0004 in the memory map
and executes code starting at the newly set value of the PC.
6.6.2
In the low-power run mode, the on-chip voltage regulator is put into its standby (or loose regulation) state.
In this state, the power consumption is reduced to a minimum that allows CPU functionality. Power
consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the
corresponding bits in the SCGC1-5 registers
Before entering this mode, the following conditions must be met:
After these conditions are met, low-power run mode can be entered by setting SPMSC2[LPR].
To re-enter standard run mode, clear the LPR bit. SPMSC2[LPRS] is a read-only status bit that can be used
to determine if the regulator is in full-regulation mode or not. When LPRS is cleared, the regulator is in
full-regulation mode and the MCU can run at full speed in any clock mode.
Assuming that SOPT1[BKGDPE] is set to enable BKGD/MS, the device also switches from LPrun to run
mode when it detects a negative transition on the BKGD/MS pin.
Low-power run mode also provides the option to return to full regulation if any interrupt occurs. This is
done by setting SPMSC2[LPWUI]. The ICS FLLs can then be set for full speed immediately in the
interrupt service routine.
6.6.2.1
Low-power run mode cannot be entered when the MCU is in active background debug mode.
If a device is in low-power run mode, a falling edge on the BKGD/MS pin exits low-power run/wait mode,
clears the LPRS bit in SPMSC2, and returns the device to normal run mode. The LPR bit remains set and
1. System clock gating control registers 1, 2, 3, 4 & 5
2. FLL bypassed external low-power
Freescale Semiconductor
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FBELP
details.
ICSC2[HGO] is cleared.
The bus frequency is less than 125 kHz.
The ADC must be in low-power mode (ADCCFG1[ADLPC] = 1) or disabled.
Low-voltage detect must be disabled. The LVDE and/or LVDSE bit in SPMSC1 register must be
cleared.
Flash programming/erasing is not allowed
Run Modes
Run Mode
Low-Power Run Mode (LPrun)
BDM in Low-Power Run Mode
2
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
is the selected clock mode for the ICS. See
1
.
Section 11.4.1, “Operational Modes,”
Modes of Operation
for more
6-7