MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 501

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MCF51EM256CLL
Manufacturer:
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Part Number:
MCF51EM256CLL
Manufacturer:
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Quantity:
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Chapter 22
Programmable Delay Block (PDB)
22.1
22.1.1
Many applications need to synchronize the time at which multiple ADC samples are taken with respect to
an external trigger or event. The primary function of the programmable delay block is simply to provide
controllable delays from the either an external trigger, or a programmable interval tick, to the sample
trigger input of one or more ADCs.
22.1.2
22.1.3
Modes of operation include:
Freescale Semiconductor
Positive transition of trigger_in will initiate the counter
Four configurable channels
— Each channel can supply two pre-trigger events to two ADC trigger select inputs.
— Each trigger output is individually controlled.
Continuous trigger or single shot mode supported
Bypass mode supported
Each trigger output can be independently enabled.
One programmable delay interrupt
One sequence error interrupt
Disabled: Counter is off and all pre-trigger and trigger outputs are low.
Enabled OneShot: Counter is enabled & restarted at count zero upon receiving a positive edge on
the trigger input. Each TriggerA and TriggerB will see only one output trigger per input trigger.
Enabled Continuous: Counter is enabled & restarted at count zero. The counter will be rolled over
to zero again when the count reaches the value specified in the MOD register, and counting
restarted. This enables a continuous stream of triggers out as a result of a single trigger input.
Bypassed: The input trigger bypasses the PDB logic entirely. It IS possible to bypass only one of
the trigger output; therefore this mode can be used in conjunction with any of the above.
Introduction
Overview
Features
Modes of Operation
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
22-1

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