MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 615

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.4.1.5.25 BDM Accesses of the MAC Registers
The presence of rounding logic in the output datapath of the MAC requires special care for BDM-initiated
reads and writes of its programming model. In particular, any result rounding modes must be disabled
during the read/write process so the exact bit-wise MAC register contents are accessed.
For example, a BDM read of the accumulator (ACC) must be preceded by two commands accessing the
MAC status register, as shown in the following sequence:
BdmReadACC (
)
Likewise, to write an accumulator register, the following BDM sequence is needed:
BdmWriteACC (
)
For more information on saving and restoring the complete MAC programming model, see
Section 9.3.1.2, “Saving and Restoring the MAC Programming Model.”
26.4.1.6
BDC commands that require CPU execution are ultimately treated at the core clock rate. Because the BDC
clock source can be asynchronous relative to the bus frequency when CLKSW is cleared, it is necessary
to provide a handshake protocol so the host can determine when an issued command is executed by the
CPU. This section describes this protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a low pulse (16 BDC clock cycles) followed by a
brief speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host,
has been successfully executed. See
ACK pulse is finished, the host can start the data-read portion of the command if the last-issued command
was a read command, or start a new command if the last command was a write command or a control
command (BACKGROUND, GO, NOP, SYNC_PC). The ACK pulse is not issued earlier than 32 BDC
clock cycles after the BDC command was issued. The end of the BDC command is assumed to be the 16th
BDC clock cycle of the last bit. This minimum delay assures enough time for the host to recognize the
ACK pulse. There is no upper limit for the delay between the command and the related ACK pulse,
because the command execution depends on the CPU bus frequency, which in some cases could be slow
compared to the serial communication rate. This protocol allows great flexibility for pod designers,
because it does not rely on any accurate time measurement or short response time to any event in the serial
communication.
Freescale Semiconductor
rcreg
wcreg
rcreg
wcreg
rcreg
wcreg
wcreg
wcreg
Serial Interface Hardware Handshake Protocol
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
macsr;
#0,macsr;
ACC;
#saved_data,macsr;// restore the original macsr
macsr;
#0,macsr;
#data,ACC;
#saved_data,macsr;// restore the original macsr
Figure
// read current macsr contents and save
// disable all rounding modes
// read the desired accumulator
// read current macsr contents and save
// disable all rounding modes
// write the desired accumulator
26-20. This pulse is referred to as the ACK pulse. After the
Version 1 ColdFire Debug (CF1_DEBUG)
26-51