MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 280

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Price
Part Number:
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Manufacturer:
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Part Number:
MCF51EM256CLL
Manufacturer:
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Quantity:
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8-bit Serial Peripheral Interface (SPI)
12.4.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
12-8
SPPR[2:0]
MODFEN
BIDIROE
SPISWAI
SPR[3:0]
Reset
SPC0
Field
Field
6:4
2:0
4
3
1
0
W
R
SPI Baud Rate Register (SPIxBR)
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to
Table 12-2
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the MOSI
(MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the output
driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
SPI Baud Rate Divisor — This 4-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
divider is the SPI bit rate clock for master mode.
0
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
12-6. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
for more details).
Table
SPPR2
0
6
12-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
Table 12-4. SPIxBR Register Field Descriptions
Table 12-3. SPIxC2 Register Field Descriptions
Figure 12-6. SPI Baud Rate Register (SPIxBR)
SPPR1
0
5
SPPR0
0
4
Figure
Description
Description
12-3).
SPR3
3
0
SPR2
0
2
Figure
Freescale Semiconductor
12-3). The output of this
SPR1
0
1
SPR0
0
0

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