MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 454

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cyclic Redundancy Check (CRC)
20.4.3
The CRC module provides an optional feature to transpose data (invert bit order). This feature is specially
useful on applications where the LSb format is used, since the CRC CCITT expects data in the MSb
format. In that case, before writing new data bytes to CRCL, these bytes should be transposed as follows:
After all data is fed into CRC, the CRCH:CRCL result is available in the MSb format. Then, these two
bytes should also be transposed: the values read from CRCH:CRCL should be written/read to/from the
TRANSPOSE register.
Although the transpose feature was initially designed to address LSb applications interfacing with the CRC
module, it is important to notice that this feature is not necessarily tied to CRC applications. Since it was
designed as an independent register, any application should be able to transpose data by writing/reading
to/from the TRANSPOSE register (e.g.: Big endian / Little endian conversion in USB).
20-8
1. Write data byte to TRANSPOSE register
2. Read data from TRANSPOSE register (subsequent reads will result in the transposed value of the
3. Write transposed byte to CRCL.
* On cycle 13, there is a read-after-write hazard, since calculation of 0x39 data is underway. ips_xfr_wait is asserted
to signalize a stall cycle (the IPS master should wait until cycle 14 to read the CRC result).
ipg_clk
ips_addr
ips_module_en
ips_rwb
ips_xfr_wait
ips_wdata
ips_rdata
last written data)
Figure 20-5. CRC calculation of ASCII message “123456789” (0x31 to 0x39) on CF1Core
Transpose feature
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
1
load seed
(0xffff)
2
0x0 0x1 0x4 0x5 0x6 0x7 0x4 0x5 0x6 0x7 0x1
0xff
3
4
0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39
write data (0x31 to 0x39),
mov.l + mov.l + mov.b
5
6
7
8
9
10
11
12
stall
cycle*
13
Freescale Semiconductor
0x0
14
read CRC
result
0x29 0xb1
15
0x1
16