MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 231

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.3
The instruction execution times for the MAC can be found in
Times”.
9.3.4
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand
type:
This format can represent numbers in the range -1 < operand < 1 - 2
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2
the most positive longword is 0x7FFF_FFFF or (1 - 2
9.3.5
MAC opcodes are described in the ColdFire Programmer’s Reference Manual.
Remember the following:
Freescale Semiconductor
Load MACSR
Store MACSR
Store MACSR to CCR
Load MAC Mask Reg
Store MAC Mask Reg
1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2
2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2
3. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
•
•
Command
< operand < 2
binary point is right of the lsb.
bits signify the first N-1 bits after the binary point. Given an N-bit number, a
its value is given by the equation in
Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that
involves the product and the accumulator.
The overflow (V) flag is managed differently. It is set if the complete product cannot be represented
as a 32-bit value (this applies to 32 × 32 integer operations only) or if the combination of the
product with the accumulator cannot be represented in the given number of bits. This indicator is
MAC Instruction Execution Times
Data Representation
MAC Opcodes
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
(N-1)
move.l {Ry,#imm},MACSR
move.l MACSR,Rx
move.l MACSR,CCR
move.l {Ry,#imm},MASK
move.l MASK,Rx
- 1. The binary point is right of the lsb.
Table 9-6. MAC Instruction Summary (continued)
value
Mnemonic
=
–
(
1 a
⋅
Equation
N 1
–
)
+
i
N 2
∑
=
–
Writes a value to MACSR
Write the contents of MACSR to a CPU register
Write the contents of MACSR to the CCR
Writes a value to the MASK register
Writes the contents of the MASK to a CPU register
9-3.
0
-31
2
–
).
(
i
+
1 N
Section 8.3.4.6, “MAC Instruction Execution
–
)
⋅
ai
(N-1)
.
Description
Multiply-Accumulate Unit (MAC)
N-1
a
N-2
a
N-3
... a
N
- 1. The
Eqn. 9-3
2
a
(N-1)
-15
1
a
9-9
0
);
,