MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 313

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.4.10.3 SPI in Stop Mode
Stop3 mode is dependent on the SPI system. Upon entry to stop3 mode, the SPI module clock is disabled
(held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the
transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is
exchanged correctly. In slave mode, the SPI will stay synchronized with the master.
The stop mode is not dependent on the SPISWAI bit.
In all other stop modes, the SPI module is completely disabled. After stop, all registers are reset to their
default values, and the SPI module must be re-initialized.
13.4.10.4 Reset
The reset values of registers and signals are described in
the registers and their bit-fields.
13.4.10.5 Interrupts
The SPI only originates interrupt requests when the SPI is enabled (SPE bit in SPIxC1 set). The following
is a description of how the SPI makes a request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
13.4.11 SPI Interrupts
There are four flag bits, three interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). The SPI match interrupt enable mask bit (SPIMIE) enables interrupts
from the SPI match flag (SPMF). When one of the flag bits is set, and the associated interrupt mask bit is
set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll
the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check
Freescale Semiconductor
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If a data transmission occurs in slave mode after reset without a write to SPIxDH:SPIxDL, it will
transmit garbage, or the data last received from the master before the reset.
Reading from the SPIxDH:SPIxDL after reset will always read zeros.
Care must be taken when expecting data from a master while the slave is in
wait or stop3 mode. Even though the shift register will continue to operate,
the rest of the SPI is shut down (i.e. a SPRF interrupt will not be generated
until exiting stop or wait mode). Also, the data from the shift register will
not be copied into the SPIxDH:SPIxDL registers until after the slave SPI has
exited wait or stop mode. A SPRF flag and SPIxDH:SPIxDL copy is only
generated if wait mode is entered or exited during a tranmission. If the slave
enters wait mode in idle mode and exits wait mode in idle mode, neither a
SPRF nor a SPIxDH:SPIxDL copy will occur.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
NOTE
Section 13.3, “Register
16-Bit Serial Peripheral Interface (SPI16)
Definition.” which details
13-27