MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 510

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Delay Block (PDB)
The signals shown in
the ADCs are independently set via the DELAYA and DELAYB parameters.
The value, modulus, is used to reset the counter back to zero at the end of the count. If PDBSC_CONT is
set, the counter will then resume a new count. Otherwise, the timer operation will cease until the next
trigger input event occurs.
In MCF51EM256 series MCUs, the PDB Channel n PreTriggerA and PreTriggerB is connected to ADCn
Trigger Select Events ADHWTSA and ADHWTSB correspondingly. Either TriggerA or TriggerB can
trigger the ADC conversion. When TriggerA triggers the ADC conversion, control and results register set
A is used; when TriggerB triggers the ADC conversion, control and results register set B is used.
The Delay A and Delay B registers should be configured to make the next trigger asserted after the
previous ADC conversion is finished.
When one conversion, triggered by TriggerA is in progress, the TriggerB output is suppressed, until the
ADCnSC1A_COCO bit is set. If Delay B is timed out during the ADC conversion triggered by TriggerA,
the Sequence Error bit PDBCHnSC_ERRB will be set.
When one conversion, triggered by TriggerB is in progress, the TriggerA output is suppressed, until the
ADCnSC1B_COCO bit is set. If Delay A is timed out during the ADC conversion triggered by TriggerB,
the Sequence Error bit PDBCHnSC_ERRA will be set.
A PDB sequence error interrupt will be generated, if any of the PDBCHnSC_ERRA or
PDBCHnSC_ERRB on any of the 4 channels is set. The sequence error interrupt cannot be disabled in
PDB module.
22-10
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
trigger input
PreTriggerA
TriggerA
PreTriggerB
TriggerB
Figure 22-10
Figure 22-10. Decoupled A & B Trigger Generation
would be used to operate on any of the 4 ADCs. The trigger delays for
Freescale Semiconductor