MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 232

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multiply-Accumulate Unit (MAC)
The following pseudocode explains basic MAC or MSAC instruction functionality. This example is
presented as a case statement covering the three basic operating modes with signed integers, unsigned
integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {},
indicates a concatenation operation.
switch (MACSR[6:5])
{
9-10
case 0:
•
if (MACSR.OMC == 0 || MACSR.V == 0)
treated as a sticky flag, meaning after set, it remains set until the accumulator or the MACSR is
directly loaded. See
The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1
indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is
added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the
MAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because
a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the
— For all left shifts, a zero is inserted into the lsb position.
then {
product is zero. For signed, longword operations, the sign bit is shifted into the product unless
an overflow occurs or the product is zero, in which case a zero is shifted in.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
MACSR.V = 0
/* select the input operands */
if (sz == word)
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if ((product[63:31] != 0x0000_0000_0) && (product[63:31] != 0xffff_ffff_1))
then {if (U/Ly == 1)
}
else {operandY[31:0] = Ry[31:0]
}
then {
/* MACSR[S/U, F/I] */
/* signed integers */
if (U/Lx == 1)
operandX[31:0] = Rx[31:0]
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
Section 9.2.1, “MAC Status Register
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
then if (product[63] == 1)
else if (MACSR.OMC == 1)
/* product overflow */
then result[31:0] = 0x7fff_ffff
else result[31:0] = 0x8000_0000
then /* overflowed MAC,
if (product[63] == 1)
saturationMode enabled */
then result[31:0] = 0x8000_0000
(MACSR)”.
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