MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 310

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Serial Peripheral Interface (SPI16)
select bits (SPR3:SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128,
256 or 512 to get the internal SPI master mode bit-rate clock.
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease I
The baud rate divisor equation is as follows except those reserved combinations in
The baud rate can be calculated with the following equation:
13.4.8
13.4.8.1
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting the SSOE and
MODFEN bits as shown in
The mode fault feature is disabled while SS output is enabled.
13.4.8.2
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see
In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit
decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and
the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and
MOSI pin in slave mode are not used by the SPI.
13-24
Special Features
SS Output
Bidirectional Mode (MOMI or SISO)
Care must be taken when using the SS output feature in a multi-master
system since the mode fault feature is not available for detecting system
errors between masters.
BUS CLOCK
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table
BaudRateDivisor
SPPR2:SPPR1:SPPR0
Figure 13-18. SPI Baud Rate Generation
1, 2, 3, 4, 5, 6, 7, or 8
Baud Rate
13-2.
PRESCALER
DIVIDE BY
=
BusClock BaudRateDivisor
NOTE
=
(
SPPR
⁄
2, 4, 8, 16, 32, 64, 128, 256 or 512
SPR3:SPR2:SPR1:SPR0
DD
+
BAUD RATE DIVIDER
1
) 2
DIVIDE BY
current.
•
(
SPR
+
1
)
Table 13-7
Freescale Semiconductor
MASTER
SPI
BIT RATE
Table
:
13-11).