MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 608

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.4.1.5.9
If the processor is halted, this command reads the selected control register and returns the 32-bit result.
This register grouping includes the PC, SR, CPUCR, MACSR, MASK, ACC, VBR, and OTHER_A7.
Accesses to processor control registers are always 32-bits wide, regardless of implemented register width.
The register is addressed through the core register number (CRN). See
when CRG is 11.
If the processor is not halted, this command is rejected as an illegal operation and no operation is
performed.
26.4.1.5.10 READ_DREG
This command reads the selected debug control register and returns the 32-bit result. This register
grouping includes the CSR, XCSR, CSR2, and CSR3. Accesses to debug control registers are always
32-bits wide, regardless of implemented register width. The register is addressed through the core register
number (CRN). See
26-44
Read CPU control register
Read debug control register
READ_CREG
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0xE0+CRN
0xA0+CRN
host →
host →
target
target
Table 26-4
D
D
L
Y
L
Y
CREG data
DREG data
for CRN details.
target →
target →
[31-24]
[31-24]
host
host
CREG data
DREG data
target →
target →
[23-16]
[23-16]
host
host
CREG data
DREG data
target →
target →
[15-8]
[15-8]
host
host
CREG data
DREG data
target →
target →
[7-0]
[7-0]
host
Table 26-24
host
Active Background
Non-intrusive
for the CRN details
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