MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 484

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC16)
If continuous conversions are enabled, a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation (ADTRG=0), continuous conversions begin after
ADCSC1A is written and continue until aborted. In hardware triggered operation(ADTRG=1 and one
ADHWTSn event has occurred), continuous conversions begin after a hardware trigger event and continue
until aborted.
If hardware averaging is enabled, a new conversion is automatically initiated after the completion of the
current conversion until the correct number of conversions is completed. In software triggered operation,
conversions begin after ADCSC1A is written. In hardware triggered operation, conversions begin after a
hardware trigger. If continuous conversions are also enabled, a new set of conversions to be averaged are
initiated following the last of the selected number of conversions.
21.5.5.2
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRHn and ADCRLn. If the compare functions are disabled, this is indicated by the setting of COCOn.
If hardware averaging is enabled, COCOn sets only if the last of the selected number of conversions is
complete. If the compare function is enabled, COCOn sets and conversion result data is transferred only
if the compare condition is true. If both hardware averaging and compare functions are enabled then
COCOn sets only if the last of the selected number of conversions is complete and the compare condition
is true. An interrupt is generated if AIENn is high at the time that COCOn is set.In all modes except 8-bit
single-ended conversions, a blocking mechanism prevents a new result from overwriting previous data in
ADCRHn and ADCRLn if the previous data is in the process of being read (the ADCRHn register has been
read but the ADCRLn register has not). When blocking is active, the conversion result data transfer is
blocked, COCOn is not set, and the new result is lost. In the case of single conversions with the compare
function enabled and the compare condition false, blocking has no effect and ADC operation is terminated.
In all other cases of operation, when a conversion result data transfer is blocked, another conversion is
initiated regardless of the state of ADCO (single or continuous conversions enabled).
21-28
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Following a hardware trigger (ADHWT) event if hardware triggered operation is selected
(ADTRG=1) and a hardware trigger select event (ADHWTSn) has occurred. The channel and
status fields selected will depend on the active trigger select signal (ADHWTSA active selects
ADCSC1A; ADHWTSn active selects ADCSC1n; if neither is active the off condition is selected).
Following the transfer of the result to the data registers when continuous conversion is enabled
(ADCO=1).
Completing Conversions
Selecting more than one hardware trigger select signal (ADHWTSn) prior
to a conversion completion will result in unknown results. To avoid this,
only select one hardware trigger select signal (ADHWTSn) prior to a
conversion completion.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
NOTE
Freescale Semiconductor