MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 189

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.7.13
This register contains control bits to enable or disable the bus clock to the flash modules. Gating off the
clocks to unused peripherals is used to reduce the microcontroller’s run and wait currents. See
“Peripheral Clock Gating,”
Freescale Semiconductor
RESERVED
Reset:
FTSR2
FTSR1
MTMI3
MTMI2
MTMI1
Field
PDB
7-2
3
2
1
0
1
0
W
R
System Clock Gating Control 5 Register (SCGC5)
PDB Clock Gate Control — This bit controls the clock gate to the PDB module.
0 Bus clock to the PDB module is disabled.
1 Bus clock to the PDB module is enabled.
MTMI3 Clock Gate Control — This bit controls the clock gate to the MTIM3 module.
0 Bus clock to the MTIM3 module is disabled.
1 Bus clock to the MTIM3 module is enabled.
MTMI2 Clock Gate Control — This bit controls the clock gate to the MTIM2 module.
0 Bus clock to the MTIM2 module is disabled.
1 Bus clock to the MTIM2 module is enabled.
MTMI1 Clock Gate Control — This bit controls the clock gate to the MTIM1 module.
0 Bus clock to the MTIM1 module is disabled.
1 Bus clock to the MTIM1 module is enabled.
RESERVED for future use. Write as all 1’s.
FTSR2 Clock Gate Control — This bit controls the bus clock gate to the flash controller #2 registers. This bit
does not affect normal program execution from the flash array. Only the clock to the flash control registers is
affected.
0 Bus clock to flash registers is disabled.
1 Bus clock to flash registers is enabled.
FTSR1 Clock Gate Control — This bit controls the bus clock gate to the flash controller #1 registers. This bit
does not affect normal program execution from the flash array. Only the clock to the flash control registers is
affected.
0 Bus clock to flash registers is disabled.
1 Bus clock to flash registers is enabled.
1
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 7-14. System Clock Gating Control 5 Register (SCGC5)
1
6
for more information.
Table 7-18. SCGC4 Bit Field Descriptions
Table 7-19. SCGC5 Bit Field Descriptions
1
5
RESERVED
1
4
Description
3
1
Resets, Interrupts, and General System Control
1
2
FTSR2
1
1
Section 7.6,
FTSR1
1
0
7-23