MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 535

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This reduces the number of driver circuits and connections to LCD segments. For multiplex mode
operation, at least two backplane drivers are needed. The LCD module is optimized for multiplex mode.
The duty cycle indicates the amount of time the LCD panel segment is energized during each LCD module
frame cycle. The denominator of the duty cycle indicates the number of backplanes that are being used to
drive an LCD panel.
The duty cycle is used by the backplane phase generator to set the phase outputs. The phase outputs A-H
are driven according to the sequence shown below. The sequence is repeated at the LCD frame frequency.
The duty cycle is configured using the DUTY[2:0] bit field in the LCDC0 register, as shown in
Table
24.4.1.2
Because a single frontplane driver is configured to drive more and more individual LCD segments, 3
voltage levels are required to generate the appropriate waveforms to drive the segment. The LCD module
is designed to operate using the 1/3 bias mode.
24.4.1.3
The LCD module is optimized to operate using a 32.768 kHz clock input. Two clock sources are available
to the LCD module, which are selectable by configuring the SOURCE bit in the LCDC0 register. The two
clock sources include:
Figure 24-11
frame frequency and blink frequency clock source. The LCD blink frequency is discussed in
Section 24.4.3.2, “Blink
Freescale Semiconductor
•
•
24-14.
External crystal —OSCOUT (SOURCE = 0)
Alternate clock (SOURCE = 1)
shows the LCD clock tree. The clock tree shows the two possible clock sources and the LCD
LCD Bias
LCD Module
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Duty
1/1
1/2
1/3
1/4
1/5
1/6
1/7
1/8
Frequency.”
DUTY2
Base Clock and
Table 24-14. LCD Module Duty Cycle Modes
0
0
0
0
1
1
1
1
LCDC0 Register
DUTY1
0
0
1
1
0
0
1
1
DUTY0
0
1
0
1
0
1
0
1
Frame Frequency
Number of Backplanes
1
2
3
4
5
6
7
8
Phase Sequence
A B C D E F G H
A B C D E F G
A B C D E F
A B C D E
A B C D
A B C
A B
A
LCD Driver Module
24-19