MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 160

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Modes of Operation
low power run mode cannot be entered again until after a system reset. Note that BKGD/MS is multiplexed
with PTC2. The pin must be configured as BKGD/MS for this operation to occur.
6.7
6.7.1
Wait mode is entered by executing a STOP instruction after configuring the device as per
execution of the STOP instruction, the CPU enters a low-power state in which it is not clocked.
The V1 ColdFire core does not differentiate between stop and wait modes. Both are stop from the core’s
perspective. The difference between the two is at the device level. In stop mode, most peripheral clocks
are shut down. In wait mode, they continue to run.
XCSR[ENBDM] must be set prior to entering wait mode if the device is required to respond to BDM
commands once in wait.
When an interrupt request occurs, the CPU exits wait mode and resumes with exception processing,
beginning with the stacking operations leading to the interrupt service routine.
6.7.2
Low-power wait mode is entered by executing a STOP instruction while the MCU is in low-power run
mode and configured per
its standby state as in the low-power run mode. In this state, the power consumption is reduced to a
minimum that allows most modules to maintain funtionality. Power consumption is reduced the most by
disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGCx registers.
Low-power run mode restrictions also apply to low-power wait mode.
If SPMSC2[LPWUI] is set when the STOP instruction is executed, the voltage regulator returns to full
regulation when wait mode is exited. The ICS FLLs can be set for full speed immediately in the interrupt
service routine.
If SPMSC2[LPWUI] is cleared when the STOP instruction is executed, the device returns to low-power
run mode.
Any reset exits low-power wait mode, clears SPMSC2[LPR], and returns the device to normal run mode.
6.7.2.1
If a device is in low-power wait mode, a falling edge on the BKGD/MS pin exits low-power run/wait
mode, clears the LPRS bit in SPMSC2, and returns the device to normal run mode. The LPR bit remains
set and low power run mode cannot be entered again until after a system reset. Again, note that BKGD/MS
is multiplexed with PTC2. The pin must be configured as BKGD/MS for this operation to occur.
6-8
Wait Modes
Wait Mode
Low-Power Wait Mode (LPwait)
BDM in Low-Power Wait Mode
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table
6-1. In the low-power wait mode, the on-chip voltage regulator remains in
Freescale Semiconductor
Table
6-1. Upon