MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 578

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power-on
Version 1 ColdFire Debug (CF1_DEBUG)
26-14
Reset
Reset
Reset
Other
COPHR
DRc: 0x02 (CSR2)
PSTBP
IOPHR
IADHR
Field
31
30
29
28
27
W
W
R
R
WDEBUG Instruction Writes CSR2[23
PSTBP
WRITE_DREG
31
15
0
0
Method
PST buffer stop. Signals if a PST buffer stop condition has been reached.
0 A PST trace buffer stop condition has not been reached
1 A PST trace buffer stop condition has been reached
Reserved, must be cleared.
Computer operating properly halt after reset. Determines operation of the device after a COP reset. This bit is
cleared after a power-on reset and is unaffected by any other reset.
0 After a computer operating properly reset, the device immediately enters normal operation mode.
1 A computer operating properly reset immediately halts the device (as if the BKGD pin was held low after a
Note: This bit may only be changed if XCSR[ENBDM] is set and the flash is unsecure.
Illegal operation halt after reset. Determines operation of the device after an illegal operation reset. This bit is
cleared after a power-on reset and is unaffected by any other reset.
0 After the device has an illegal operation reset, the device immediately enters normal operation mode.
1 An illegal operation reset immediately halts the device (as if the BKGD pin was held low after a power-on reset).
Note: This bit may only be changed if XCSR[ENBDM] is set and the flash is unsecure.
Illegal address halt after reset. Determines operation of the device after an illegal address reset. This bit is cleared
after a power-on reset and is unaffected by any other reset.
0 After the device has an illegal address reset, the device immediately enters normal operation mode.
1 An illegal address reset immediately halts the device (as if the BKGD pin was held low after a power-on reset).
Note: This bit may only be changed if XCSR[ENBDM] is set and the flash is unsecure.
power-on reset).
30
14
0
0
0
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
COP
HR
Unaffected and Undefined
29
13
0
u
Writes CSR2[23
a privileged supervisor-mode instruction.
Figure 26-5. Configuration/Status Register 2 (CSR2)
Table 26-8. CSR2 Reference Summary (continued)
IOP
HR
PSTBWA
28
12
0
u
IAD
HR
Table 26-9. CSR2 Field Descriptions
27
11
0
u
–
–
0] from the BDM interface. Classified as a non-intrusive BDM command.
0] during the core’s execution of WDEBUG instruction. This instruction is
26
10
0
0
0
BFHBR
25
0
u
9
BDFR
Description
24
Reference Details
0
0
0
8
PSTBH
PSTBR
23
0
0
0
0
7
DIV16
APC
22
PSTBST
0
0
0
6
21
0
0
0
0
5
20
PSTBRM
0
0
0
0
4
Access: Supervisor read-only
Freescale Semiconductor
19
0
0
3
0
18
0
0
2
0
D1HRL
BDM read/write
PSTBSS
17
0
0
0
1
16
1
1
0
0