MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 634

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision History
A.3
A-2
System Control
Analog-to-Digit
Interrupts, and
Internal Clock
Source (ICS)
Connections
Independent
al Converter
Throughout
Reference
Real Time
Controller
Overview
Pins and
(ADC16)
Chapter
Interrupt
Chapter
Memory
General
Resets,
Voltage
Device
Clock
Changes Between Rev. 6 and Rev. 7
Changed the vector of number 67 to PDB_err in the
Correct the ENB bit status after reset to 1 in the
Added an interrupt source of PDB_err in Level 7 Priority 1 of
Updated the MODE description.
Updated pinout information to PTB0/RGPIO8/KBI1P0/PRACMP2P0/RX2 and
PTB2/RGPIO10/KBI1P2/PRACMP1P0/RX1.
Changed all the robust RTC to IRTC.
Updated the version of IRTC and GPIO in the
Added a note to the
Updated the register information at address 0x(FF)FF_845D, 0x(FF)FF_849D, and 0x(FF)FF_84DD
Corrected the heading information to COP window Opens (SOPT1[COPW] = 1) in the
Configuration
Updated the reset information of bit 4 in the
Updated the description of PMC_LVD_TRIM in the
Updated “any change of state on these pins will indicate a tamper” to “high level input on this pin will indicate a
tamper” in the
Corrected the reset to information of Bit 0 in the
Updated “Any state change on these bits is considered as a tamper and an interrupt is generated to CPU.” to
“High level input on this pin is considered as a tamper and an interrupt is generated if the tamper interrupt is
enabled.”
Updated the title of
Updated
Removed “Calibration is recommended to be done after any reset.” in the
Added “For best calibration results it is recommended to set hardware averaging to maximum (AVGE=1,
AVGS=11 for average of 32), ADC clock frequency fADCK less than or equal to 4 MHz, VREFH=VDDAD and
to calibrate at nominal voltage and temperature.” and removed “hardware average function,” in the
Section 21.5.7, “Calibration
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table A-2. MCF51EM256RM Rev. 5 to Rev. 6 Changes (continued)
Table 21-1 ADC Channel
Details.
Section 17.4,
Table A-3. MCF51EM256RM Rev. 6 to Rev. 7 Changes
Table 11-1 ICS Clock Check and Select Block
Table 2-23 ADC Pinout
Freescale Confidential Proprietary
Function.”
“Overview.”
Assignments.
Summary.
Figure 7-7 System Options 2 Register
Table 1-4 Versions of On-Chip
Figure
Figure 17-13 IRTC Interrupt Enable Register
Description
Description
Table 7-12 SOPT2 Bit Field
Table
10-4.
10-2.
Table
Diagram.
10-12.
Section 21.5, “Functional
Modules.
Descriptions.
(SOPT2).
Freescale Semiconductor
Table 7-11 COP
(IRTC_IER).
Description.”