MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 601

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
DUMP_MEM.sz_WS
FILL_MEM.sz
FILL_MEM.sz_WS
GO
NOP
READ_CREG
READ_DREG
READ_MEM.sz
READ_MEM.sz_WS
READ_PSTB
READ_Rn
READ_XCSR_BYTE
READ_CSR2_BYTE
READ_CSR3_BYTE
Command
Mnemonic
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Classification
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Background
Background
Command
Available
Available
Available
Always
Always
Always
Active
Active
Table 26-25. BDM Command Summary (continued)
if Enb?
ACK
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
1
(0x31+4 x sz)/ad24/d/ss/rd.sz Read the appropriately-sized (sz) memory
(0x30+4 x sz)/ad24/d/rd.sz
(0x13+4 x sz)/wd.sz/d/ss
(0x33+4 x sz)/d/ss/rd.sz
(0x12+4 x sz)/wd.sz/d
(0xE0+CRN)/d/rd32
(0xA0+CRN)/d/rd32
(0x40+CRN)/d/rd32
(0x60+CRN)/d/rd32
Command
Structure
0x2D/rd8
0x2E/rd8
0x2F/rd8
0x08/d
0x00/d
Dump (read) memory based on operand
size (sz) and report status. Used with
READ_MEM{_WS} to dump large blocks of
memory. An initial READ_MEM{_WS} is
executed to set up the starting address of
the block and to retrieve the first result.
Subsequent DUMP_MEM{_WS}
commands retrieve sequential operands.
Fill (write) memory based on operand size
(sz). Used with WRITE_MEM to fill large
blocks of memory. An initial WRITE_MEM
is executed to set up the starting address of
the block and to write the first operand.
Subsequent FILL_MEM commands write
sequential operands.
Fill (write) memory based on operand size
(sz) and report status. Used with
WRITE_MEM{_WS} to fill large blocks of
memory. An initial WRITE_MEM{_WS} is
executed to set up the starting address of
the block and to write the first operand.
Subsequent FILL_MEM{_WS} commands
write sequential operands.
Resume the CPU’s execution
No operation
Read one of the CPU’s control registers
Read one of the debug module’s control
registers
Read the appropriately-sized (sz) memory
value from the location specified by the
24-bit address
value from the location specified by the
24-bit address and report status
Read the requested longword location from
the PST trace buffer
Read the requested general-purpose
register (An, Dn) from the CPU
Read the most significant byte of the debug
module’s XCSR
Read the most significant byte of the debug
module’s CSR2
Read the most significant byte of the debug
module’s CSR3
Version 1 ColdFire Debug (CF1_DEBUG)
Description
3
26-37