MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 569

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

While in halt mode, the core waits for serial background commands rather than executing instructions from
the application program.
Figure 26-2
controls the BDC clock source. When CLKSW is set, the BDC serial clock frequency is half the CPU
clock. When CLKSW is cleared, the BDC serial clock is supplied from an alternate clock source.
The ENBDM bit determines if the device can be placed in halt mode, if the core and BDC serial clocks
continue to run in STOP modes, and if the regulator can be placed into standby mode. Again, if booting to
halt mode, XCSR[ENBDM, CLKSW] are automatically set.
If ENBDM is cleared, the ColdFire core treats the HALT instruction as an illegal instruction and generates
a reset (if CPUCR[IRD] is cleared) or an exception (if CPUCR[IRD] is set) if execution is attempted.
If XCSR[ENBDM] is set, the device can be restarted from STOP/WAIT via the BDM interface.
26.2
Table 26-3
is shown in
Freescale Semiconductor
Background Debug
Illegal address reset and CSR2[IADHR]=1 or
(BKGD)
Illegal op reset and CSR2[IOPHR]=1 or
Signal
COP reset and CSR2[COPHR]=1 or
External Signal Descriptions
(POR or BDFR=1) with BKGD=0 or
describes the debug module’s 1-pin external signal (BKGD). A standard 6-pin debug connector
Section 26.4.4, “Freescale-Recommended BDM
contains a simplified view of the V1 ColdFire debug mode states. The XCSR[CLKSW] bit
BDFR, BFHBR, and BKGD=1 or
BDFR=1 and BFHBR=0 or
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
BDFR and BFHBR= 1 or
POR with BKGD=1 or
any other reset
Single-wire background debug interface pin. The primary function of this pin is for bidirectional serial
communication of background debug mode commands and data. During reset, this pin selects
between starting in active background (halt) mode or starting the application program. This pin also
requests a timed sync response pulse to allow a host development tool to determine the correct clock
frequency for background debug serial communications.
CPU clock/2 is used
Figure 26-2. Debug Modes State Transition Diagram
as the BDM clock
BDM & CPU clocks are not
enabled in STOP modes
State
Any
Debug not enabled
Table 26-3. Debug Module Signals
CLKSW=1
CLKSW=0
ENBDM=1
ENBDM=0
Operation
Normal
Debug
Halt
Description
clear ENBDM
command
BDM GO
Pinout”.
via BDM
BACKGROUND command,
ENBDM
ENBDM=1
Operation
Normal
HALT instruction, or
Set
Version 1 ColdFire Debug (CF1_DEBUG)
Return to Halt via
BDM breakpoint trigger
CPU clocks continue
during STOP modes
Debug is enabled
26-5