MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 618

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
attempting to send any new command that requires CPU execution. This prevents the new command from
being discarded at the debug/CPU interface, due to the pending command being executed by the CPU. Any
new command should be issued only after XCSR[CSTAT] is cleared.
There are multiple reasons that could cause a command to take too long to execute, measured in terms of
the serial communication rate: The BDC clock frequency could be much faster than the CPU clock
frequency, or the CPU could be accessing a slow memory, which would cause pipeline stall cycles to occur.
All commands referencing the CPU registers or memory require access to the processor’s local bus to
complete. If the processor is executing a tight loop contained within a single aligned longword, the
processor may never successfully grant the internal bus to the debug command. For example:
label1: nop
or
label2: bra.w
These two examples of tight loops exhibit the BDM lockout behavior. If the loop spans across two
longwords, there are no issues, so the recommended construct is:
label3: bra.l
The hardware handshake protocol is appropriate for these situations, but the host could also decide to use
the software handshake protocol instead. In this case, if XCSR[CSTAT] is 001, there is a BDC command
pending at the debug/CPU interface. The host controller should monitor XCSR[CSTAT] and wait until it
is 000 to be able to issue a new command that requires CPU execution. However, if the XCSR[CSTAT] is
1xx, the host should assume the last command failed to execute. To recover from this condition, the
following sequence is suggested:
Figure 26-22
command could be issued by the host.
26-54
1. Issue a SYNC command to reset the BDC communication channel.
2. The host issues a BDM NOP command.
3. The host reads the channel status using a READ_XCSR_BYTE command.
4. If XCSR[CSTAT] is 000
then the status is okay; proceed
else
align
bra.b
align
align
shows a SYNC command aborting a READ_MEM.B. After the command is aborted, a new
Halt the CPU using a BDM BACKGROUND command
Repeat steps 1,2,3
If XCSR[CSTAT] is 000, then proceed, else reset the device
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
4
label1
4
label2
4
label3
Figure 26-22
signal timing is not drawn to scale.
NOTE
Freescale Semiconductor