MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 252

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Controller (CF1_INTC)
10.6.1
As noted in
masking is controlled by CCR[I], the interrupt mask flag: clearing CCR[I] enables interrupts, while setting
CCR[I] disables interrupts. The ColdFire architecture defines seven interrupt levels, controlled by the 3-bit
interrupt priority mask field in the status register, SR[I], and the hardware automatically supports nesting
of interrupts.
To emulate the HCS08’s 1-level IRQ capabilities on V1 ColdFire, only two SR[I] settings are used:
The ColdFire core treats the level seven requests as non-maskable, edge-sensitive interrupts.
ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This
allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
contained in the status register as the first instruction in the ISR. In addition, the V1 instruction set
architecture (ISA_C) includes an instruction (STLDSR) that stores the current interrupt mask level and
loads a value into the SR. This instruction is specifically intended for use as the first instruction of an
interrupt service routine that services multiple interrupt requests with different interrupt levels. For more
details see the ColdFire Family Programmer’s Reference Manual. A MOVE-to-SR instruction also
performs a similar function.
To emulate the HCS08’s 1-level IRQ nesting mechanisms, the ColdFire implementation enables interrupts
by clearing SR[I] (typically when using RTE to return to a process) and disables interrupts upon entering
every interrupt service routine by one of three methods:
10.6.2
Section 10.3.2, “INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}),”
control registers that provide the ability to dynamically alter the request level and priority of two IRQs.
Specifically, these registers provide the ability to reassign two IRQs to be the highest level 6 (maskable)
requests. Consider the following example.
Suppose the system operation desires to remap the receive and transmit interrupt requests of a serial
communication device (SCI1) as the highest two maskable interrupts. The default assignments for the
SCI1 transmit and receive interrupts are:
To remap these two requests, the INTC_PL6P{7,6} registers are programmed with the desired interrupt
source number:
10-16
•
•
1. Execution of STLDSR #0x2700 as the first instruction of an ISR.
2. Execution of MOVE.w #0x2700,SR as the first instruction of an ISR.
3. Static assertion of CPUCR[IME] that forces the processor to load SR[I] with seven automatically
•
•
Writing 0 to SR[I] enables interrupts.
Writing 7 to SR[I] disables interrupts.
upon the occurrence of an interrupt exception. Because this method removes the need to execute
multi-cycle instructions of #1 or #2, this approach improves system performance.
sci1_rx = interrupt source 20 = vector 84 = level 4, priority 3
sci1_tx = interrupt source 21 = vector 85 = level 4, priority 2
Emulation of the HCS08’s 1-Level IRQ Handling
Using INTC_PL6P{7,6} Registers
Table
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
10-1, the HCS08 architecture specifies a 1-level IRQ nesting capability. Interrupt
Freescale Semiconductor
describes