MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 586

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.3.8
The PBRn registers define instruction addresses for use as part of the trigger. These registers’ contents are
compared with the processor’s program counter register when the appropriate valid bit is set (for PBR1–3)
and TDR is configured appropriately. PBR0 bits are masked by setting corresponding PBMR bits (PBMR
has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined
in TDR. The PC breakpoint registers, PBR1–3, have no masking associated with them, but do include a
26-22
L1EPC
L1PCI
L1ED
Field
L1EA
12–6
L1DI
4–2
5
1
0
Enable level 1 data breakpoint. Setting an L1ED bit enables the corresponding data breakpoint condition based on
the size and placement on the processor’s local data bus. Clearing all L1ED bits disables data breakpoints.
Level 1 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a
trigger based on the occurrence of a data value other than the DBR contents.
0 No inversion
1 Invert data breakpoint comparators.
Enable level 1 address breakpoint. Setting an L1EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the address breakpoint.
Enable level 1 PC breakpoint.
0 Disable PC breakpoint
1 Enable PC breakpoint
Level 1 PC breakpoint invert.
0 The PC breakpoint is defined within the region defined by PBRn and PBMR.
1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.
Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
TDR Bit
TDR Bit
Table 26-14. TDR Field Descriptions (continued)
12
11
10
4
3
2
9
8
7
6
Enable address breakpoint inverted. Breakpoint is based
outside the range between ABLR and ABHR.
Enable address breakpoint range. The breakpoint is based on
the inclusive range defined by ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the
address in the ABLR.
Data longword. Entire processor’s local data bus.
Lower data word.
Upper data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
Description
Description
Description
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