MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 547

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.4.4.1
Using the voltage divider and charge pump, the LCD module can effectively double or triple the input
voltage placed on the V
both 3-V or 5-V LCD glass.
The LCD module high reference select bit (HREFSEL) in the LCDSUPPLY register configures the LCD
module operational mode as a voltage doubler or a voltage tripler. In
is used to control switches within the voltage divider block to enable or disable the two-thirds (2/3 * V
voltage divider. If HREFSEL = 0, the LCD module is configured as a voltage doubler, by enabling the
voltage divider. With this configuration if V
1.5 V * 2/3 = 1 V = V
V
V
If HREFSEL = 1, the LCD module is configured as a voltage tripler by disabling the voltage divider. (V
= V
application.
24.4.4.1.1
The CPSEL bit in the LCDSUPPLY register selects the charge pump. When the charge pump is selected
(CPSEL = 1), V
When the charge pump is unselected (CPSEL = 0), V
by a resistor bias network.
24.4.4.2
The LCD bias voltages can be internally derived from V
not exceed V
configured to supply 1.0 or 1.67 V (V
range between .9 to 1.8 V that is applied to the V
of the power state of the LCD module which depends on the configuration of the
VSUPPLY[1:0],HREFSEL, BBYPASS, CPSEL and RVEN bits.
Table 24-22
configuration bits above are not permissible LCD power supply modes and should be avoided.
Freescale Semiconductor
LL1
LL1
LCD
* 2 = 2 V = V
* 3 = 3 V = V
) The HREFSEL configuration depends on the LCD panel operating voltage specification in the
shows all possible configurations of the LCD Power Supply. All other combinations of the
DD
LCD Charge Pump and Voltage Divider
LCD Power Supplyand Voltage BufferConfiguration
During the first 16 timebase clock cycles after the LCDCPEN bit is set, all
the LCD frontplane and backplane outputs are disabled, regardless of the
state of the LCDEN bit.
The charge pump requires external capacitance for its operation. To provide
this external capacitance, the V
recommended that a ceramic capacitor be used. Proper orientation is
imperative when using a polarized capacitor. The recommended value for
the external capacitor is 0.1 μF.
CPSEL: LCD Charge Pump or Resistor Bias Enable
LL1
) connected to V
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
, V
LL2
LL3
LL1
LL2
LCD
, and V
pin.This LCD module configurability makes the LCD module compatible with
LL3
LL3
, internally derived from a regulated voltage source that can be
are generated internally.
IREG
), or it can be internally derived from a voltage source in the
LCD
cap1 and
LCD
= 1.5 V the bias voltages generated will be:V
pin.
V
LL3
cap2
DD
Table 24-22
must be supplied and V
, internally derived from a voltage source (must
external pins are provided. It is
provides a more detailed description
Figure
24-15, HREFSEL bit signal
LL1
, V
LL2
LCD Driver Module
are generated
LCD
* 2/3 =
LCD
24-31
LL1
)