MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 225

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Field
OMC
Reset:
S/U
R/T
F/I
BDM: Read: 0xE4 (MACSR)
N
7
6
5
4
3
2
Z
W
R
Write: 0xC4
OMC
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set
to the appropriate constant (see S/U field description) on any operation that overflows the accumulator.
After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the
overflow bit is cleared or the accumulator is directly loaded.
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the accumulator
value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, the accumulator saturates to the most positive
1 Unsigned numbers. On overflow, if OMC is enabled, the accumulator saturates to the smallest value
In fractional mode:
S/U controls rounding while storing the accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to
Fractional/integer mode. Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to
Round/truncate mode. Controls rounding procedure for MSAC.L instructions when in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
0
7
(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the
product value that overflowed.
(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
register as a 32-bit value.
a general-purpose register. See
lower word of the destination register. The upper word is zero-filled. This rounding procedure does not
affect the accumulator value.
1 - 2
Representation."
32-bit value. If the low-order 32 bits equal 0x8000_0000, the upper 32 bits are rounded to the nearest
even (lsb = 0) value. See
-15
for 16-bit fractions and -1 to 1 - 2
S/U
6
0
Figure 9-2. MAC Status Register (MACSR)
Table 9-2. MACSR Field Descriptions
F/I
Section 9.3.1.1,
0
5
Section 9.3.1.1,
R/T
0
4
-31
“Rounding”.
Description
for 32-bit fractions. See
“Rounding”. The resulting 16-bit value is stored in the
N
0
3
Z
0
2
Section 9.3.4, “Data
Access: Supervisor read/write
Multiply-Accumulate Unit (MAC)
V
0
1
BDM read/write
C
0
0
9-3